The present invention relates to integrated circuit design and fabrication. More specifically, the present invention pertains to a method and system for maximizing the production of integrated circuit dies by varying die dimensions during design to maximize gross die per wafer and minimize stepper shot count during fabrication.
Integrated circuit dies are fabricated en masse on silicon wafers using well-known techniques such as photolithography. Using these techniques, a pattern that defines the size and shape of the components and interconnects within a given layer of the die is applied to the wafer. The pattern applied to the wafer is laid out in an array, or matrix, of reticle images. A wafer stepper holds the pattern over a wafer and projects the pattern image of the reticle onto the wafer. The area on the wafer upon which the image is projected is defined as a stepper shot. A multitude of interconnecting layers, one formed on top of another, are essentially built up on the integrated circuit dies using several passes through the stepper.
The gross number of dies that can be produced from a single wafer is, as would be expected, dependent on the size and shape of the individual dies. The number of stepper shots is dependent on the number of die images that can be placed in the printable field of the reticle, which in turn is dependent on the size and shape of the individual dies. Therefore, the number of stepper shots is also dependent on the size and shape of the individual dies.
Prior Art FIG. 1 illustrates a wafer 10 on which a pattern of dies, exemplified by die 22, have been laid out. In this example, die 22 is square shaped. If the size or shape of die 22 were changed, then the number of dies that would fit on wafer 10 would likely change.
Shot 20, in this example, consists of a five-by-five (5xc3x975) die matrix that projects a shot image on a 5xc3x975 array of dies. Consider the second row from the top of wafer 10. This row consists of five 5xc3x975 arrays of dies, and so would require five 5xc3x975 stepper shots to complete. A sixth stepper shot could be made onto region 30 of wafer 10; however, this sixth shot would not result in a total 5xc3x975 array of dies being formed because region 30 is not of sufficient size, and so a portion of the sixth shot would overrun past the edge of the wafer. For the purpose of discussion, assume that the sixth shot forms six additional dies in region 30. Thus, for the first five shots, the output would be 25 dies per shot, while for the sixth shot, the output would be six dies. Therefore, the sixth shot, comprising an increase of 20 percent in the number of shots made, results in an increase of only about five percent in the number of dies produced.
Accordingly, it may not always be desirable to maximize the number of dies produced per wafer. If the fabrication facility wafer steppers are not being used to capacity, then it generally is appropriate to maximize the gross number of dies per wafer. On the other hand, if the fabrication facility is capacity limited by its wafer steppers, it may be more important to minimize the stepper shot count. When the fabrication facility is fully loaded, it may be beneficial to accept slightly fewer dies per wafer if the number of stepper shots is reduced as a result, thereby allowing more wafers to be processed during a given time frame and consequently producing a greater number of total dies.
However, the prior art is problematic because decisions may be made in the design phase without fully considering the effect on the fabrication phase. In the prior art, the design phase and the fabrication phase of the integrated circuit die production process may be separate and independent from each other. In the design phase, the integrated circuit die must be designed to have a surface area large enough to accommodate the microcircuitry that will be included in the integrated circuit. The designer will typically choose dimensions that provide a size and shape that provide the required surface area, but may pay lesser regard to selecting dimensions that, along with providing the required surface area, also maximize the gross number of dies per wafer.
In some instances in the prior art, an effort may be made to coordinate the design phase with the fabrication phase. Generally, this effort consists of relatively informal discussions between the various departments involved. As might be expected, this coordination may not always take place. However, even in those cases where a more formal process is used to coordinate design and fabrication, the prior art is still problematic because the dimensions of the die are often chosen with the goal of maximizing the number of dies per wafer, without considering the number of stepper shots needed to produce the dies. As described above, it is not always desirable to maximize the number of dies produced per wafer.
Accordingly, what is needed is a method and/or system that can facilitate coordination between the design and fabrication phases of integrated circuit die production. What is also needed is a method and/or system that can accomplish the above need and that can be readily implemented at the front-end (i.e., the design phase or the like) of the die production process. Furthermore, what is needed is a method and/or system that can accomplish the above needs and can maximize the rate of die production based on either or both the number of dies per wafer and the number of stepper shots, depending on the desired utilization of the fabrication facility. The present invention provides a novel solution to the above needs.
These and other objects and advantages of the present invention will become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
The present invention provides a method and system thereof that can facilitate coordination between the design and fabrication phases of integrated circuit die production. The present invention also provides a method and system thereof that can be readily implemented at the front-end (i.e., the design phase or the like) of the die production process. Furthermore, the present invention provides a method and system thereof that can maximize the rate of die production based on either or both the number of dies per wafer and the number of stepper shots, depending on the desired utilization of the fabrication facility.
The present embodiment of the present invention pertains to a method and system thereof for maximizing integrated circuit die production. A wafer size, scribe lane width and dimensions for a die are received. A die count (e.g., the gross number of die per wafer) and a stepper shot count corresponding to the dimensions are determined using one or more lookup tables. A lookup table is associated with each combination of wafer size and scribe lane width. A measure of die production is calculated using the die count and the stepper shot count. The dimensions can be changed and a new measure of die production calculated using the changed dimensions, until a maximum value of the measure of die production is determined.
In one embodiment, the measure of die production is determined by dividing the die count by the stepper shot count.
In one embodiment, an identifier is used to indicate a type of integrated circuit die production method, and the scribe lane width associated with this identifier is retrieved from a database and used with the lookup tables to determine the die count and the stepper shot count.
In one embodiment, the method is implemented on a server computer system in a client-server computer system network. In this embodiment, the server computer system receives from a client computer system the wafer size, scribe lane width, and die dimensions. The measure of die production is calculated and transmitted to the client computer system.
In one embodiment, to generate the lookup tables, a range of die lengths and widths is specified, and an initial value of die length and width is selected from within the range. An identifier indicating a type of stepper is received, and a stepper field size limit associated with the identifier is retrieved from a database. A die matrix of reticle images is modeled using the stepper field size limit, the length and width for a die, and a scribe lane width. A die count is calculated for each of a plurality of different offsets of the die matrix measured relative to a fixed location on a wafer. The optimum value of these die counts is selected and stored in a first lookup table. A stepper shot count is calculated for the offset corresponding to the optimum die count and stored in a second lookup table. Similar calculations are performed for the range of different die lengths and widths in order to build the lookup tables.